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? semiconductor components industries, llc, 2018 june, 2018 ? rev. 0 1 publication order number: NCP12700/d NCP12700 ultra wide input current mode pwm controller the NCP12700 is a fixed frequency, peak current mode, pwm controller containing all of the features necessary for implementing single?ended power converter topologies. the device features a high voltage startup capable of operating over a wide input range and supplying at least 15 ma to provide temporary bias to v cc during system startup. the device contains a programmable oscillator capable of operating from 100 khz to 1 mhz and integrates slope compensation to prevent subharmonic oscillations. the controller offers an adjustable soft?start, input voltage uvlo protection, and an adjustable over?power protection circuit which limits the total power capability of the circuit as the input voltage increases, easing the system thermal design. the uvlo pin also features a shutdown comparator which allows for an external signal to disable switching and bring the controller into a low quiescent state. the NCP12700 contains a suite of protection features including cycle?by?cycle peak current limiting, timer?based overload protection, and a flt pin which can be interfaced with an ntc and an auxiliary winding to provide system thermal protection and output over?voltage protection. all protection features place the device into a low quiescent fault mode and recovery from fault mode is dependent on the device option. common general features ? wide input range (9 ? 120/200 v; msop10/wqfn10) ? startup regulator circuit with 15 ma capability ? current mode control with integrated slope compensation ? suitable for flyback or forward converters ? single resistor programmable oscillator ? 1 a / 2.8 a source / sink gate driver ? user adjustable soft?start ramp ? input voltage uvlo with hysteresis ? shutdown threshold for external disable ? skip cycle mode for low standby power ? this is a pb?free device fault protection features ? user adjustable over?power protection ? overload protection with 30 ms overload timer ? ntc?compatible fault interface for thermal protection ? output ovp fault interface ? fault auto?recovery mode with 1 s auto?recovery period typical applications ? single?ended power converters including ccm/dcm flyback and forward converters ? telecommunications power converters ? industrial power converter modules ? transportation & railway power modules www. onsemi.com marking diagrams wqfn10 mt suffix case 511dv see detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ordering information msop dn suffix case 846ae 1 12700 or 700 = specific device code x = a or b a = assembly site ll = wafer lot number yw = assembly start week = pb?free package 12700x allyw 1 10 700x ayw (note: microdot may be in either location)
NCP12700 www. onsemi.com 2 figure 1. typical application circuit for vin = 12 ? 160 v figure 2. typical application circuit for vin = 9 ? 18 v feedback with isolation gnd vcc drv cs comp vin rt flt vout vin ss uvlo feedback with isolation gnd vcc drv cs comp vin rt flt vout vin ss uvlo
NCP12700 www. onsemi.com 3 figure 3. block diagram 9 7 3 2 8 5 6 4 1 10 vdrv osc rt vdd drv flt clk fault logic d max gnd ss ss control ovld i flt i ss vdd v comp(skip) v comp(skip_hys) main logic vccon enable fault start v ss fault shdn ss_end c cc v cc vin regulation hv startup internal regulator vdd vdrv vcc logic vccon vcc(ovp) vcc(ovp) vcc(uvlo) vcc(uvlo) uvlo i uvlo(hys) comp v ss vdd 5k 1/6 1/6 cs uvlo detection shdn enable over?power protection i cs(opp) leb block vdd i cs(opp) pwm logic slope comp ovld s q r clk drv stop start d max ss_end start tsd tsd tsd stop
NCP12700 www. onsemi.com 4 vin vcc drv gnd cs uvlo flt ss rt comp vin vcc drv gnd cs uvlo flt ss rt comp pinouts (top views) ep table 1. pin function description msop10 wqfn10 pin name pin description 1 9 uvlo the uvlo pin is the input to the standby and uvlo comparators. a resistor divider between the power supply input voltage and ground is connected to the uvlo pin to set the input volt- age level at which the controller will be enabled. uvlo hysteresis is set by a 5 a pull?down current source. an externally supplied pull?down signal can also be used to disable the con- troller. the uvlo pin is also used to determine the over?power protection current supplied to the cs pin. 2 10 flt the flt pin is the input to a window comparator which provides an upper and lower fault threshold. when either threshold is tripped, the controller enters the fault mode which can be a permanent latch off or a minimum 1 s auto?recovery period. a precision current source is out- put from the flt pin allowing an ntc to ground to be placed at the pin for system over?tem- perature protection. the upper threshold can be used for output over?voltage protection sensed through the auxiliary winding or as a general purpose fault. 3 1 ss the ss pin sets the soft?start ramp of the peak current limit when the controller is enabled. an internal 15 a current source and an external capacitor to ground are used to control the ramp rate. typical soft start capacitor values will be in the range of 10 nf to 100 nf. 4 2 rt the rt pin sets the oscillator frequency in the controller. this pin requires a resistor to ground located close to the ic. typical rt values are in the range of 10 k ? 100 k . 5 3 comp the comp pin provides the compensated error voltage for the pwm and skip comparators. an internal 5 k pull?up resistor is connected to the comp pin and can be used to bias the transistor of an opto?coupler. 6 4 cs the cs pin is the current sense input for the pwm and current limit comparators. the com- parator input is held low for 60 ns after the drv goes high to prevent leading edge current spikes from tripping the comparators. an external low pass filter is recommended for improved noise immunity. the external filter resistor is also used to determine the amount of over?pow- er protection applied to the current sense. 7 5 gnd this pin is the controller ground. for the wqfn package the exposed pad (ep) should be connected to gnd. 8 6 drv the drv pin is a high current output used to drive the external mosfet gate. drv has source and sink capability of 1 a and 2.8 a, respectively. 9 7 vcc the vcc pin provides bias to the controller. an external decoupling capacitor to ground in the range of 1 ? 10 f is recommended. 10 8 vin the vin pin is the input to the high voltage startup regulator. the regulator is capable of sourc- ing > 15 ma to temporarily bias vcc while the application is starting up. ordering information device package otp fault ovp fault shipping ? NCP12700adnr2g msop10 latch latch 4000 / tape & reel NCP12700bdnr2g msop10 autorecovery autorecovery 4000 / tape & reel NCP12700bmttxg wqfn10 autorecovery autorecovery 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
NCP12700 www. onsemi.com 5 table 2. maximum ratings rating symbol value unit high voltage startup voltage (msop10) (wqfn10) v in(max) 120 200 v high voltage startup current i in(max) 50 ma supply voltage v cc(max) ?0.3 to 30 v supply current i cc(max) 50 ma drv voltage (note 1) v drv(max) ?0.3 v to v drv(high) v drv current (peak) i drv(max) 3.25 a flt voltage v flt(max) v cc + 1.25 v flt current i flt(max) 10 ma max voltage on signal pins v sig(max) ?0.3 to 5.5 v max current on signal pins i sig(max) 10 ma thermal resistance junction?to?air (note 2) (msop10) (wqfn10) r j?a 165 51 c/w junction?to?top thermal characterization parameter (msop10) (wqfn10) j?c 10 12 c/w maximum junction temperature t jmax 150 c maximum power dissipation (msop10) (wqfn10) p d internally limited w storage temperature range t stg ?55 to 150 c operating temperature range t j ?40 to 125 c esd capability (note 3) human body model per jedec standard jesd22?a114e charge device model per jedec standard jesd22?c101e 2000 1000 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. maximum driver voltage is limited by the driver clamp voltage, v drv(high) , when v cc exceeds the driver clamp voltage. otherwise, the maximum driver voltage is v cc . 2. per jedec specification jesd51.7 using two 1 oz copper planes with board size = 80x80x1.6 mm 3. this device series contains esd protection and exceeds the following tests: human body model 2000 v per jedec standard jesd22?a114e charge device model tbd per jedec standard jesd22?c101e 4. this device contains latch?up protection and has been tested per jedec jesd78d, class i and exceeds +/?100 ma (tbd). table 3. recommended operating conditions rating symbol value unit vin voltage (msop10) (wqfn10) v in 9 ? 100 12 ? 160 v supply voltage ? all v cc 9 ? 20 v v operating temperature range t j ?40 to 125 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability.
NCP12700 www. onsemi.com 6 table 4. electrical characteristics (v in = 12 v, v cc = 12 v, v comp = open, v flt = open, c drv = 1 nf, r t = 49.9k , v cs = 0 v, v ss = open, v uvlo = 1.2, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics test condition symbol min typ max unit high voltage startup regulator regulated voltage v cc = open, i cc = 5 ma v cc(reg) 7.6 8 8.4 v current source capability v in = 9 v, v cc = 7 v i vin(src) 15 ma current source limit v cc = v cc(off) + 100 mv i vin(lim) 30 ma off?state leakage current (xmttxg) v cc = open, v in = 160 v, v uvlo = 0 i vin(off) 100 a off?state leakage current (xdnr2g) v cc = open, v in = 120 v, v uvlo = 0 i vin(off) 100 a supply circuit supply voltage startup threshold minimum operating voltage v cc increasing v cc decreasing v cc(on) v cc(off) v cc(reg) ? 350 mv 6.2 6.5 v cc(reg) ? 100 mv 6.8 v supply over?voltage protection v cc(ovp) 28 v vcc ovp detection filter delay t vccovp (dly) 3 s startup delay measured from v cc(on) to ss t on(dly) 25 s supply current shdn stby enable fault v uvlo = 0 v v uvlo = 0.7 v c drv = open, v comp = 2 v v flt = 0 v i cc(shdn) i cc(stby) i cc(en) i cc(flt) ? ? ? ? ? ? ? ? 50 750 4 500 a a ma a current sense current limit comparator threshold v cs(lim) 465 495 525 mv propagation delay from current sense limit to drv low step v cs from 0 ? 0.6 v t cs(dly) ? ? 75 ns short circuit protection (scp) current limit threshold v scp(lim) 625 mv propagation delay from short circuit limit to drv low v cs = 0.75 v t scp(dly) ? ? 75 ns short circuit counter v cs = 0.75 v n scp 4 cs leading edge blanking (leb) t leb(cs) 75 100 125 ns scp leading edge blanking t leb(scp) 45 60 75 ns cs leb pull?down resistance r pd(leb) ? 55 overload timer duration v cs = 0.6 v t cs(ovld) 24 30 36 ms applied slope compensation @ cur- rent limit comparator v comp = open; measured at d 80% v slp(ilim) 83 102 123 mv duty cycle where slope compensat- ing ramp begins d 40% 40 % comp section pwm to comp gain through resistor divider v comp = 2 v k pwm 6 pwm propagation delay to drv low v comp = 2 v, step from cs 0? 0.4 v t pwm(dly) ? 75 ns comp open pin voltage v comp(open) 4 4.7 v comp output current v comp = 0 i comp 0.84 1 1.2 ma maximum duty cycle v comp = open d max 76 80 84 % comp skip threshold v comp(skip) 300 mv
NCP12700 www. onsemi.com 7 table 4. electrical characteristics (v in = 12 v, v cc = 12 v, v comp = open, v flt = open, c drv = 1 nf, r t = 49.9k , v cs = 0 v, v ss = open, v uvlo = 1.2, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol test condition comp section comp skip hysteresis v comp (skip_hys) 25 mv minimum duty cycle v comp = 0 d min 0 % applied slope compensation @ pwm comparator v comp = 2 v; measured at d 80% v slp(pwm) 77 98 117 mv soft start soft?start open pin voltage v ss(open) 5.0 v soft?start end threshold v ss(end) 2.85 3 3.15 v soft?start current v ss = 3 v i ss 12 15 18 a soft?start to cs divider k ss 6 soft?start discharge resistance r ss(dis) 100 oscillator oscillator frequency 1 f osc1 185 200 215 khz oscillator frequency 2 r t = 100 k f osc2 95 100 105 khz oscillator frequency 3 r t = 20 k f osc3 450 500 550 khz oscillator frequency 4 r t = 9.09 k f osc4 1000 khz under?voltage lockout (uvlo) standby threshold v uvlo increasing v stby(th) 0.35 0.5 0.65 v reset threshold v uvlo decreasing v rst(th) 0.3 0.45 0.6 v standby hysteresis v uvlo decreasing v stby(hys) 50 mv standby detection rc filter t stby(dly) 5 s uvlo threshold v uvlo increasing v uvlo(th) 765 800 830 mv uvlo threshold hysteresis v uvlo decreasing v uvlo(hys) 15 mv uvlo hysteresis current i uvlo(hys) 4.5 5 5.5 a uvlo detection delay filter v uvlo = v uvlo(th) ? 20 mv t uvlo(dly) 0.5 1 s over?power protection (opp) uvlo voltage above which opp ap- plied v opp(start) 1 v opp gain gm (opp) 135 150 165 a / v maximum current (operating point) v uvlo = 2.33 v i cs(opp1) 180 200 220 a maximum current v uvlo = 4 v i cs (opp_max) 200 a comp threshold voltage above which opp is applied v opp(0%) 0.8 v comp threshold voltage for 100% opp v opp(100%) 2 v gate drive drv rise time v drv = 1.2 v to 10.8 v t drv(rise) 6 10 15 ns drv fall time v drv = 10.8 v to 1.2 v t drv(fall) 2.5 4 10 ns drv source current v drv = 6 v i drv(src) 1.0 a drv sink current v drv = 6 v i drv(snk) 2.8 a drv clamp voltage v cc = 20 v, r drv = 10 k v drv(clamp) 10 12 14 v
NCP12700 www. onsemi.com 8 table 4. electrical characteristics (v in = 12 v, v cc = 12 v, v comp = open, v flt = open, c drv = 1 nf, r t = 49.9k , v cs = 0 v, v ss = open, v uvlo = 1.2, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol test condition gate drive minimum drv voltage v cc = v cc(off) + 100 mv, r drv = 10 k v drv(min) 6 v fault protection fault source current i flt 80 85 90 a otp fault threshold v flt(otp) 0.47 0.5 0.53 v otp detection filter delay t otp(dly) 10 20 30 s otp fault recovery threshold v flt(rec) 0.846 0.9 0.954 v ovp fault threshold v flt(ovp) 2.8 3 3.2 v ovp detection filter delay t ovp(dly) 3 5 7 s fault clamp voltage v flt = open v flt(clamp) 1.13 1.35 1.57 v fault clamp resistance r flt(clamp) 1.6 k auto?recovery timer t ar 0.8 1 1.2 s thermal shutdown thermal shutdown t shdn 150 165 180 c thermal shutdown hysteresis t shdn(hys) 25 c
NCP12700 www. onsemi.com 9 application information the NCP12700 is a fixed frequency, peak current mode, pwm controller containing all of the features necessary for implementing single?ended power converter topologies. the device features an ultra?wide range, high voltage startup regulator capable of regulating v cc across an input voltage range of 9 ? 120 v (xdnr2g) or 9 ? 200 v (xmttxg). the controller is designed for high speed operation including a programmable oscillator capable of operating from 100 khz to 1 mhz and total propagation delays less than 75 ns in the pwm path. the NCP12700 integrates slope compensation to prevent subharmonic oscillations and an input voltage compensation / over?power protection (opp) feature that limits the converter power delivery capability across input voltage, easing system thermal design. the controller offers an adjustable soft?start, input voltage uvlo protection, and a suite of protection features including cycle?by?cycle current limit and a flt pin with a ntc interface for system thermal protection. the uvlo pin also features a shutdown comparator which allows for an externally applied pull?down signal to disable switching and bring the controller into a low quiescent state. ultra?wide range hv startup regulator the NCP12700 features a high voltage startup regulator capable of operating across input voltage ranges of 9?120 v (xdnr2g) or 9?200 v (xmttxg). the ultra?wide range capability of the regulator allows for direct connection of vin to the converter input voltage without requiring external components. the regulator?s input voltage capabilities support a wide range of industrial, medical, telecom, and transportation applications. figure 4 details the operation of the startup regulator. when vin is applied, the regulator will immediately begin sourcing current to charge v cc . initially the startup will supply approximately 10 ma. once v cc builds up to ~ 3 v, the control loop for the hv regulator will activate and the source current will be regulated to 30 ma until v cc reaches the v cc(reg) level of 8 v. the hv startup is a linear regulator which can continue to supply and regulate v cc at 8 v. the recommended v cc capacitance to ensure stability of the regulator is 1 ? 10 f. while the v cc voltage is below the v cc(on) threshold the controller will remain in a low quiescent state to allow for rapid charging of v cc and fast startup of the application. once the v cc voltage reaches the v cc(on) threshold, approximately 200 mv below the v cc(reg) level, the controller will exit the low quiescent state and begin delivering drive pulses. while the output voltage is building up, the startup regulator will continue to supply the current necessary to maintain v cc at the v cc(reg) level. for low input voltage applications, the startup regulator has been designed to guarantee a minimum of 15 ma source capability with 2 v of headroom. in typical applications an auxiliary winding will be used to provide bias to v cc once the converter is switching. this allows for the most efficient operation of the system. once the auxiliary winding pulls the v cc voltage above v cc(reg) , the hv regulator will shut off. in normal operation the v cc voltage can be biased above the voltage at vin and can support voltages up to 28 v. a v cc ovp protection feature will trigger at 28 v, disabling switching of the converter to prevent the auxiliary winding voltage from damaging the controller.
NCP12700 www. onsemi.com 10 figure 4. startup timing diagram output voltage time v cc(off) v cc(reg) v cc v in = 12 v v cc(on) v cc = 3 v i vin i vin = 30 ma i vin ~ 10 ma i vin = i cc once the device has begun delivering drive pulses it will remain active as long as v cc remains above the v cc(off) threshold of 6.5 v. either the auxiliary winding or the hv startup regulator will provide the bias necessary to keep v cc above this level. if v cc does drop below the v cc(off) threshold the controller will inhibit drive pulses, the device will reset and once again enter a low quiescent state. this should only occur if the input voltage to the converter has been removed but can also be an indication of excessive external loading on v cc . input voltage uvlo detection the NCP12700 features line voltage uvlo detection to ensure that the converter becomes operational only after meeting a minimum input voltage threshold thereby protecting the converter from thermal stress at low input voltages. a functional block diagram of the uvlo detection circuitry is shown in figure 5. the input line voltage is monitored through a resistor divider network allowing the user to set the thresholds for when to enable and disable the converter. typical pull?down resistors in the divider network will be in the range of 5 ? 20 k and pull?up resistors will typically be in the range of 50 ? 500 k . external capacitive filtering on the order of 10 nf is also advisable. when input voltage is initially applied to the converter the device will be in a shutdown/reset (shdn) state until the uvlo voltage crosses the v stby(th) threshold of 0.5 v. in the shdn state the device consumption will be limited to the i cc(shdn) value of 50 a. when the uvlo voltage goes above v stby(th) the device transitions into standby mode and the consumption increases to the i cc(stby) limit of 750 a maximum. the low current consumption in the shutdown and standby modes allow v cc to rapidly charge to the v cc(on) threshold. once v cc has charged to v cc(on) the device will enable drive pulses when the uvlo voltage exceeds the v uvlo(th) of 0.8 v and disables drive pulses when the uvlo voltage falls below 0.8 v by v uvlo(hys) . prior to enabling drive pulses the device also activates a pull?down current source, i uvlo(hys) , of 5 a. the current source works in combination with v uvlo(hys) to set the input voltage hysteresis for enabling and disabling switching operation of the converter. a resistor, r uvlo(hys) , can be used to provide additional hysteresis between the enable and disable thresholds. equation 1 and equation 2 can be used to calculate the necessary component values in the resistor divider network.
NCP12700 www. onsemi.com 11 figure 5. uvlo block diagram v uvlo(th) uvlo enable v stby(th) stby shdn i uvlo(hys) r uvlo1 r uvlo2 v in 5 s v rst(th) s r q q r uvlo(hys) v in,start v uvlo(th) r uvlo1 r uvlo2 r uvlo1 r uvlo2 r uvlo(hys) i uvlo(hys) r uvlo1 r uvlo2 r uvlo2 (eq. 1) v in,stop v uvlo(th) v uvlo(hys) r uvlo1 r uvlo2 r uvlo2 (eq. 2) input voltage compensation / over?power protection p 0.5 l i 2 p i 2 v f sw (eq. 3) in a ccm flyback converter the output power capability is defined by equation 3 where i p is the peak transformer current, i v is the valley or minimum transformer current, l is the primary inductance, and f sw is switching frequency. in a dcm flyback converter the valley current becomes 0 and equation 3 still applies. the peak current capability of the converter can be impacted by several variables including input voltage and the operating duty cycle due to the internal slope compensation in the NCP12700. managing the peak current limit over the operating input voltage range will limit the total power capability and ease system thermal design. the NCP12700 features the input voltage compensation / over?power protection (opp) circuitry shown in figure 6. the over?power protection circuit functions as a transconductance amplifier which senses an image of the input line voltage through the uvlo pin. when the uvlo voltage crosses the v opp(start) threshold, typically 1 v, the ota begins sourcing a current out of the cs pin. the current injected out of the cs pin will be according to equation 4 where the typical transconductance, g m(opp) , is 150 a/v and the maximum current is limited to the i cs(opp_max) value of 200 a. i cs(opp) g m(opp) v uvlo v opp(start) (eq. 4) good smps design practice for current mode control includes a small rc filter in series between the current sense resistor and the cs pin of the controller. typical values for the resistor in the rc filter are 500 ? 1 k . the user can then limit the peak current capability of the converter by setting the r cs resistor value and can reduce the peak current capability of the converter by 20 ? 40% with these values. figure 6. over?power protection diagram uvlo v in cs drv i cs(opp) comp r uvlo1 r uvlo2 r sns r cs v opp(start) v dd c cs
NCP12700 www. onsemi.com 12 another aspect of the over?power protection feature is that the current sourced out of the cs pin is modulated as a function of the comp voltage to ensure that the current is only available when necessary. this is detailed in figure 7 below with typical values for v opp(0%) = 0.8 v and v opp(100%) = 2 v. the typical values of 0.8 v and 2 v equate to ~ 27% and 67% of the full load capability of the device, hence the opp current should begin being applied at 27% load an d should ramp up to 100% opp current at 67% load. figure 7. opp current profile vs. comp voltage time 0.8 v v comp 100% 2 v 0 i cs(opp)
NCP12700 www. onsemi.com 13 pwm operation rt pin & oscillator the oscillator in the NCP12700 uses an external resistor from the rt pin to ground to set the switching frequency of the converter. the frequency set by the rt resistor follows f osc 1 rt 100 10 ?12 (eq. 5) where f osc is the switching frequency. the curve in figure 8 below shows the oscillator frequency vs. rt resistor for values between ~10 k to 100 k . the NCP12700 is designed to operate between 100 khz and 1 mhz but will have tighter tolerance at lower switching frequencies. figure 8. oscillator frequency vs. rt resistor value 0 100 200 300 400 500 600 700 800 900 1,000 0 102030405060708090 oscillator frequency (khz) 100 rt resistor value (k) gate driver (drv) the NCP12700 is equipped with a gate driver for driving the primary side mosfet. the driver applies v cc up to the clamped voltage, v drv(clamp) , of 12 v as a high signal and 0 v to the gate of the power mosfet as a low signal. the rate of charging and discharging of the gate of the mosfet is dependent upon the input capacitance of the mosfet and the impedance of the driver. the NCP12700 is equipped with an i drv(src) pull?up current, typically 1 a, and a pull down current of i drv(snk) , typically 2.8 a ensuring fast turn on/off transitions of the power mosfet and minimizing the switching losses. pwm reset path the NCP12700 is intended for isolated dc?dc converters where the control loop compensation circuitry is located on the secondary side of the power converter. the converter output voltage is compared against a reference voltage and an error amplifier produces a compensated error signal which is communicated to the NCP12700 through an optocoupler. the compensated error signal interfaces with the comp pin where it is divided down by a 5r/r voltage divider and sent to the pwm s/r to modulate the switching duty cycle. a detailed functional diagram of the pwm path is shown in figure 9. the pwm comparator compares the attenuated error signal from the comp pin to the current ramp signal sensed at the cs pin to determine when the drive pulse should be terminated. this comparator serves as the primary modulation path for the converter duty cycle.
NCP12700 www. onsemi.com 14 figure 9. NCP12700 pwm path pwm logic s q r vdd comp pwm comparator cs current limit comparator skip comparator v cs(lim) leb v comp(skip) vdd drv clk t cs(ovld) ovld 5r r 5k v comp(skip_hys) i cs(opp) slope compensation slope compensation drv scp comparator t leb(cs) t leb(scp) v scp(lim) counter n scp scp scp soft?start comparator 1/6 ss switching disabled vdd i ss d max figure 10. slope compensation timing diagram drv v slp v pwm 0 d 80% d 40% slope compensation in fixed frequency peak current mode control, converters operating at duty cycles greater than 50% of the switching period are susceptible to sub?harmonic oscillation, characterized by successive switching cycles with alternating wide and narrow pulse?widths. to avoid sub?harmonic oscillation the NCP12700 implements an internal slope compensation circuit which is applied to the attenuated comp signal at the input of the pwm comparator. the slope compensation timing diagram is shown in figure 10. the compensating ramp begins reducing the
NCP12700 www. onsemi.com 15 attenuated comp voltage when the switching duty cycle is nominally 40% and reduces the voltage by a peak, v slp(pk) , of 98 mv at the 80% duty cycle limit. the slope compensating r amp is synchronized to the duty cycle of the oscillator, ef fectively adjusting itself based on the switching frequency, providing the converter with a compensating dv/dt ramp appropriate for the particular switching frequency. an image of the slope compensating ramp is also applied at the input of the current limit comparator to prevent sub?harmonic oscillations from occurring during overload conditions. the chart below summarizes the dv/dt of the compensating ramp at some common operating frequencies. f sw (khz) t sw ( s) d = 40% ( s) d = 80% ( s) v slp (mv) ramp (mv/ s) 100 10.00 4.00 8.00 98 25 200 5.00 2.00 4.00 98 49 250 4.00 1.60 3.20 98 61 330 3.03 1.21 2.42 98 81 400 2.50 1.00 2.00 98 98 500 2.00 0.80 1.60 98 123 cycle?by?cycle current limit and overload protection the NCP12700 implements cycle?by?cycle current limiting with a dedicated current limit comparator. the input to the comparator is the primary fet current ramp sensed at the cs pin. if the sensed voltage exceeds the current limit threshold, v cs(lim) , of 495 mv then the drive pulse is terminated. the current limit comparator is very fast with a total propagation delay, t cs(dly) , of 75 ns maximum ensuring that drive pulses are quickly terminated minimizing current overshoot in the converter. the current limit comparator also triggers an overload timer, t cs(ovld) , nominally 30 ms, and will disable drive pulses and take the device into a fault mode when the timer has expired. the 30 ms timer allows the converter to sustain a short term overload but still protects the converter from thermal overstress in the event of a continuously applied overload condition. the overload timer is also an integrating timer, it will continue ramping up while the current limit comparator is terminating drive pulses but will begin ramping down, not reset completely, if the drive pulse is terminated by another signal such as the pwm comparator. this operation is depicted in figure 11. figure 11. integrating overload timer v comp v drv overload timer time t 1 t 2 t 3 t 4 t 5 t 6 short circuit (scp) comparator the NCP12700 also includes a fast short circuit comparator with a threshold, v scp(lim) , of 625 mv. in certain extreme fault conditions such as a shorted secondary side rectifier or a shorted winding in the transformer it may be possible to sense an abnormally high current pulse at the cs pin and disable drive pulses to prevent the converter from
NCP12700 www. onsemi.com 16 further damage. if the voltage at the cs pin rapidly exceeds 625 mv and the scp comparator trips, then the drive pulse will be terminated and a counter will be incremented. if the scp comparator trips on 4 consecutive drive pulses then drive pulses will be disabled and the controller is put into the fault mode. leading edge blanking (leb) converters operating in peak current mode control require a high quality current ramp signal to ensure stable and clean pwm operation. in the NCP12700 the current ramp signal is sensed at the cs pin and is routed through a leb circuit which blanks the current sense information for a brief period after the drv voltage is delivered to the primary mosfet. the leb prevents noise generated during the switching transition from terminating drive pulses prematurely. the blanking is performed by an internal pulldown switch and series disconnect switch. the internal pulldown switch has an on resistance, r pd(leb) , specified as 55 ohms maximum. the pulldown switch is turned on whenever the drv is low and remains on for a period of time equal to t leb(scp) , 60 ns typical, after the drv is set high. after t leb(scp) has expired the current ramp signal is delivered to the scp comparator allowing it to sense an abnormal overcurrent situation. a longer series leb, t leb(cs) , of 100 ns continues to hold open the signal path to the cs and pwm comparators. this switch closes when t leb(cs) has expired, allowing the cs information to be delivered to the other two comparators. in addition to the leb network, the user of the controller will usually place a small rc filter in between the current sense components and the cs pin to provide noise suppression. the resistor value in the rc filter is typically in the range of 500 ? 1 k , sized appropriately for the over?power protection feature, and the capacitor value is typically chosen to provide a time constant for the rc filter of about 50 ? 100 ns. skip comparator for a power converter operating at light loads it is sometimes desired to skip drive pulses in order to maintain output voltage regulation or improve the light load efficiency of the system. the NCP12700 features a dedicated skip comparator which monitors the voltage at the comp pin and blanks drive pulses if the comp voltage falls below the v comp(skip) threshold of 300 mv. to re?enable new drive pulses, the comp voltage must exceed a skip hysteresis, v comp(skip_hys) of 25 mv above the 300 mv threshold. the skip hysteresis is designed to prevent the converter from oscillating in and out of skip mode due to noise on the comp pin. maximum duty cycle the NCP12700 also includes a maximum duty cycle clamp which terminates a drive pulse which has been high for d max of the switching period. the default value of d max will be 80%. soft start the soft start feature in the NCP12700 is implemented with a dedicated comparator that compares the current ramp signal from the cs pin against an attenuated soft start ramp generated at the ss pin. prior to enabling switching, an internal pull?down transistor with an on resistance, r ss(dis) , of 100 is activated to discharge the external soft start capacitor and hold the ss pin to gnd. once switching is enabled the pull?down transistor is released and a current source, i ss , of 15 a charges the soft start capacitor forming the soft start ramp voltage. the soft start ramp voltage is then divided down by a factor of 6 and fed into the soft start comparator which resets drive pulses when the cs voltage exceeds the soft start voltage. the soft start comparator will continue to reset drive pulses until another comparator enters the reset path which typically occurs when the secondary side control loop responds allowing the pwm comparator to take control. the NCP12700 monitors the external soft start voltage and sets a flag when the voltage exceeds 3 v, declaring that the soft start period has ended. at 3 v, the drive pulse reset control will have been handed off to either the pwm comparator or the current limit comparator. the ss_end flag is used internally by the controller for fault management, gating detection of certain faults that may be erroneously triggered during power up of the converter. this is shown in the flt pin block diagram of figure 12. figure 12. flt pin block diagram vdd v flt(otp) ss_end i flt to fault logic v flt(ovp) v flt(otp_hys) t otp(dly) t ovp(dly) to v cc
NCP12700 www. onsemi.com 17 fault (flt) pin the flt pin is intended to provide the system with a ntc interface for thermal protection and a pull?up fault which can be coupled to the auxiliary winding to provide output over?voltage protection. the flt pin can also be used as a general purpose fault where it interfaces with a simple pull?down bjt , open collector comparator, or optocoupler for monitoring of secondary side faults. the internal circuitry includes a precision pull?up current source, i flt , of 85 a and a window comparator to signal a fault whenever the pin voltage goes below the otp fault threshold, v flt(otp) , of 0.5 v or above the ovp fault threshold, v flt(ovp) , of 3 v. both of the fault comparators also include a delay filter to prevent noise or glitches from setting the fault. the over?temperature fault filter, t otp(dly) , is nominally 20 s and the over?voltage fault filter, t ovp(dly) , is typically 5 s. an external filter capacitor is also advisable. both faults have an option to permanently latch off the controller or restart after a 1 s auto?recovery period. the ovp fault is intended to monitor an auxiliary winding and when triggered, the controller will disable switching which will inhibit the aux winding from generating voltage and allow the controller to restart after the auto?recovery timer has expired. if the ovp fault comparator is continuously held above 3 v, the NCP12700 will remain in the fault mode and not restart. the otp fault detection is gated by the ss_end flag to prevent the comparator from triggering while the external filter capacitor charges up. once the ss_end flag is set the otp fault can be acknowledged so there is a practical limit on the size of the filter capacitor. equation 6 and equation 7 should assist the user with properly setting the external capacitance of the fault pin. t ss_end c ss v ss_end i ss (eq. 6) c flt i flt t ss_end v flt(otp) (eq. 7) when the otp fault is triggered the NCP12700 will again disable drive pulses and transition into a fault mode. the otp fault is auto?recoverable based on the auto?recovery timer and a hysteresis set by the v flt(rec) threshold of 0.9 v. the auto?recovery timer must expire and the voltage at the fault pin must exceed 0.9 v. this methodology guarantees a minimum amount of time for the system to recover from thermal overstress but will not allow the converter to restart unless the hysteresis is met. given the i flt and v flt(otp) specifications the critical ntc resistance for declaring a fault is ~ 5.9 k . the critical resistance for recovering from the otp fault becomes ~ 10.6 k . this fault recovery threshold provides for about ~20 c of hysteresis for many ntc resistors. summary of fault handling the NCP12700 has 6 fault detectors which will place the device into the fault mode. in the fault mode switching is inhibited and the controller bias is maintained by the hv startup regulator. the controller also reduces current consumption to i cc(flt) , 500 a maximum, so that the regulator is not thermally overstressed. the NCP12700 remains in the fault mode until the fault signal has been cleared and/or the auto?recovery timer has expired. the fault signal can be cleared when the fault detector senses that the fault has been removed or by a controller reset which occurs if v cc drops below v cc(off) or the uvlo pin is pulled below the v rst(th) level. below is a brief summary of the different fault detectors and their basic operation. ? thermal shutdown (tsd): thermal shutdown is declared when the internal junction temperature of the device exceeds the t shdn temperature of 165 c. the thermal shutdown fault is auto?recoverable when the device junction temperature reduces to t shdn ? t shdn(hys) where t shdn(hys) is typically 25 c. ? fault otp: an otp fault is declared when fault pin voltage decreases below the v flt(otp) threshold of 0.5 v and the otp filter, t otp(dly) , expires. the otp filter delay is typically 20 s. the otp fault is blanked at startup until the ss_end flag has been set to allow the external capacitance of the pin to charge up. for the device to recover from the fault otp, the auto?recovery timer must expire and the voltage at the fault pin must recover to v flt(rec) value of 0.9 v. ? fault ovp: the ovp fault is declared when fault pin the voltage exceeds the v flt(ovp) threshold of 3 v and the ovp filter, t ovp(dly) , expiring. the ovp filter delay is typically 5 s. the ovp fault is cleared when the auto?recovery timer expires. there is no hysteresis on the ovp fault but if the pin voltage is permanently held above 3 v, drv will pulses will be permanently inhibited. ? overload (ovld): the ovld fault is set when the overload timer, t ovld , expires. the overload timer is an integrating timer which counts up as long as the current limit comparator is terminating drv pulses. the typical value for t ovld is 30 ms. the controller will recover from the ovld fault when the auto?recovery timer expires. ? scp fault: the scp fault occurs when the n scp counter has reaches 4 consecutive drv pulses terminated by the scp comparator. the controller will recover from the scp fault when the auto?recovery timer expires. ? v cc ovp: the v cc ovp is set when v cc voltage exceeds the v cc(ovp) threshold of 28 v and the v cc ovp filter, t vcc_ovp(dly) , expires. the v cc ovp filter is typically 3 s. v cc ovp will permanently latch the device off so that it remains in the fault mode indefinitely until the controller is reset.
NCP12700 www. onsemi.com 18 evaluation board designs two evaluation boards have been developed to highlight the features of the NCP12700. detailed schematics, operating waveforms, and bill of materials are available in the design notes, dn05108 and dn05109. dn05108 describes the operation of a 9 ? 36 v input flyback converter delivering 12 v out at 15 w. this evaluation board switches at 200 khz and operates in both continuous and discontinuous conduction modes. the key performance specifications are shown in table 5 below. table 5. low voltage flyback evaluation board specifications evaluation board # 1 vin 9 ? 36 v operating vo 12 v ? 1.25 a po 15 w specifications startup time < 30 ms full load efficiency > 87 % transient response < 250 s over power protection 120% ? 150% over voltage protection 16 vdc max no load output ripple 200 mvpp max no load power dissipation 120 mw max input current in shdn < 1 ma dn05109 describes the operation of a 18 ? 160 v input flyback converter delivering 12 v out at 15 w. this demonstration board switches at 100 khz and operates in discontinuous conduction mode across the entire input voltage range. the key performance specifications are shown in table 6. table 6. wide range flyback evaluation board specifications evaluation board # 2 vin 18 ? 160 v operating vo 12 v ? 1.25 a po 15 w specifications startup time < 20 ms full load efficiency > 85 % transient response < 250 s over power protection 115% ? 155% over voltage protection 16 vdc max no load output ripple 150 mvpp max no load power dissipation 500 mw max input current in shdn < 1 ma
NCP12700 www. onsemi.com 19 package dimensions msop10, 3x3 case 846ae issue a notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.10 mm in excess of maximum material condition. 4. dimension d does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. dimension e does not include inter- lead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. dimensions d and e are determined at datum f. 5. datums a and b to be determined at datum f. 6. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. dim min nom millimeters a ??? ??? a1 0.00 0.05 b 0.17 ??? c 0.13 ??? d 2.90 3.00 l2 0.25 bsc e 0.50 bsc l 0.40 0.70 l1 0.95 ref e 4.75 4.90 e1 2.90 3.00 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* recommended a m 0.08 b c s s f c 0.10 c detail a 10x 0.85 5.35 0.50 pitch 10x 0.29 dimensions: millimeters max 1.10 0.15 0.27 0.23 3.10 0.80 5.05 3.10 a2 0.75 0.85 0.95 0 ??? 8 l1
NCP12700 www. onsemi.com 20 package dimensions case 511dv issue a notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.20 and 0.25mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the plated terminals. dim min nom millimeters a 0.70 0.75 a1 0.00 0.025 k 0.30 ref a3 k1 0.36 ref b 0.25 0.30 d 3.90 4.00 e 0.80 bsc d1 1.75 1.80 d b e a top view side view bottom view c a a1 seating plane c 0.08 c 0.10 e k1 e1 d1 b note 3 1 4 7 10 10x pin one reference *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended e 2.90 3.00 detail b note 4 detail a a m 0.10 b c m 0.05 c soldering footprint* l1 0.05 ref l1 detail a l alternate terminal constructions l ?? ?? 1.53 1.58 l 0.30 0.35 max 0.80 0.05 0.35 4.10 1.85 3.10 1.63 0.40 dimensions: millimeters 10x 0.40 1.80 1.58 1.59 3.60 10x 0.65 2x 0.36 0.80 pitch 0.30 4.60 e l 10x k 3 0.20 ref on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 NCP12700/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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